1. Field of the Invention
This invention relates to a semiconductor device and method for manufacturing it, for example to a semiconductor memory device including capacitorless DRAM memory cells and a method for manufacturing it.
2. Related Art
A conventional DRAM memory cell of a DRAM includes a capacitor for storing signal charges and a switching transistor (for example, a MOSFET or other FETs). Capacitance of the capacitor required to store signal charges is generally about 30 fF. It is necessary to keep this capacitance of the capacitor of about 30 fF for a DRAM to maintain stable operation, even if the reduced design rule for the DRAM is adopted due to improvement in a degree of cell integration. Therefore, the DRAM memory cell of a conventional DRAM generally have required process improvement for miniaturizing a capacitor, such as thinning an insulating film for a capacitor of stack type or trench type.
On the contrary, a capacitorless DRAM has been proposed. In a DRAM memory cell of the capacitorless DRAM, a transistor (for example, a MOSFET or other FETs) is necessary, but a capacitor is not required. Therefore, the DRAM memory cell of the capacitorless DRAM may have less possibility to hinder improvement in a degree of cell integration.
A specific example of the capacitorless DRAM memory cell includes an FBC (Floating Body Cell) described in Japanese Patent Laid-Open No. 2002-246571. The FBC described in Japanese Patent Laid-Open No. 2002-246571 includes an FET formed on an SOI substrate. To realize the memory cell, the FBC described in Japanese Patent Laid-Open No. 2002-246571 utilizes a phenomenon associated with the change in the threshold voltage of the FET depending on whether or not holes are present in the channel region of the FET.
We will consider a case where an FBC is used as a memory cell, and the memory cell and an element other than a memory cell are formed on a substrate. In this case, it is conceivable to provide an SOI region and a bulk region on a SOI substrate, to form the memory cell and the element other than a memory cell on the SOI region and the bulk region respectively. This allows a device structure having the memory cell and the element other than a memory cell, as if they were formed on a typical SOI substrate and a typical bulk substrate respectively.
The above device structure has the following advantages over a device structure in which a memory cell and an element other than a memory cell are formed on a typical SOI substrate. Firstly, it is not necessary to alter design environment (such as a SPICE MODEL) of the element other than a memory cell, from that for a bulk substrate to that for an SOI substrate, allowing improved device development efficiency. Secondly, high voltage transistor characteristics and ESD characteristics of an input/output circuit and the like of the element other than a memory cell are improved. Thirdly, the above-mentioned device structure ensures specification continuity with a conventional device structure in which the element other than a memory cell is formed on a typical bulk substrate.
When an FBC is used as a memory cell, and the memory cell and an element other than a memory cell are formed on a substrate, employing a typical SOI substrate as the substrate and employing a special SOI substrate having an SOI region and a bulk region as the substrate have a common feature that an SOI substrate needs to be prepared. The former SOI substrate can be prepared, for example, by purchasing a commercially available SOI substrate. The latter SOI substrate can be prepared, for example, by converting part of the SOI region in a commercially available SOI substrate into a bulk region using a semiconductor process.
However, a commercially available SOI substrate is extremely expensive compared to a commercially available bulk substrate. At present, a commercially available SOI substrate costs approximately 5 to 10 times higher than a commercially available bulk substrate. On the other hand, when a substrate similar to a commercially available SOI substrate is manufactured in house using a similar process for manufacturing a commercially available SOI substrate, tremendous efforts will be required.
Therefore, when an FBC is used as a memory cell, and the memory cell and an element other than a memory cell are formed on a substrate, although employing the latter SOI substrate as the substrate, instead of employing the former SOI substrate, is conceivably very effective, the cost and effort associated with preparing the SOI substrate becomes a bottleneck.
This problem of the cost and effort associated with preparing an SOI substrate similarly becomes a bottleneck, when a memory cell is formed on an SOI substrate but an element other than a memory cell is not formed thereon.